FPGA implementation of fast QR decomposition based on givens rotation

Author

Aslan, Semih ; Niu, Sufeng ; Saniie, Jafar

Author_Institution

Dept. of Electr. & Comput. Eng., Texas State Univ., San Marcos, TX, USA

fYear

2012

fDate

5-8 Aug. 2012

Firstpage

470

Lastpage

473

Abstract

In this paper, an improved fixed-point hardware design of QR decomposition, specifically optimized for Xilinx FPGAs is introduced. A Givens Rotation algorithm is implemented by using a folded systolic array and the CORDIC algorithm, making this very suitable for high-speed FPGAs or ASIC designs. We improve the internal cell structure so that the system can run at 246MHz with nearly 24M updates per second throughout on a Virtex5 FPGA. The matrix size can be easily scaled up.

Keywords

digital arithmetic; field programmable gate arrays; logic design; systolic arrays; ASIC designs; CORDIC algorithm; FPGA implementation; Givens rotation; Virtex5 FPGA; Xilinx FPGA; fast QR decomposition; fixed-point hardware design; folded systolic array; frequency 246 MHz; high-speed FPGA; internal cell structure; Arrays; Feedback loop; Field programmable gate arrays; Mathematical model; Matrix decomposition; Microprocessors; FPGA; QR decomposition; givens rotation; systolic;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Conference_Location

Boise, ID

ISSN

1548-3746

Print_ISBN

978-1-4673-2526-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2012.6292059

Filename

6292059