DocumentCode
3205707
Title
FIFO locked loop control system
Author
Bassan, Fabio Renato ; de Camargo Angeli, B.C. ; de Barros, Luis Paulo F. ; Mobilon, Eduardo
Author_Institution
Opt. Syst. - Electron. & Microelectron., CPqD - Telecom R&D Centre, Campinas, Brazil
fYear
2012
fDate
5-8 Aug. 2012
Firstpage
566
Lastpage
569
Abstract
In this paper we present a methodology for the development of a circuit to control the reading frequency of a First In First Out (FIFO) memory based on the monitoring of its filling level, with applications in data communication protocol justification architectures for tributary signal mapping and demapping.
Keywords
data communication; memory cards; protocols; FIFO locked loop control system; data communication protocol justification architectures; filling level monitoring; first in first out memory; reading frequency; tributary signal demapping; tributary signal mapping; Control systems; Equations; Filling; Frequency control; Mathematical model; Payloads; Pulse width modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location
Boise, ID
ISSN
1548-3746
Print_ISBN
978-1-4673-2526-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2012.6292083
Filename
6292083
Link To Document