Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis

In the presence of process variation, conventional worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. As a result, statistical static timing analysis (SSTA) is essentially needed in high-level synthesis (HLS) stage. This paper presents the first work to develop a design framework of SSTA for HLS based on transparent latches. An integer linear programming-based formal approach is provided to simultaneously solve scheduling and functional unit binding to minimize the scheduling length while meeting the timing-yield requirement. Experiments demonstrate the effectiveness of the proposed approach.