• DocumentCode
    3206501
  • Title

    Embedded LO synthesis method in harmonic rejection mixers

  • Author

    Forbes, Travis ; Gharpurey, Ranjit

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
  • fYear
    2012
  • fDate
    5-8 Aug. 2012
  • Firstpage
    750
  • Lastpage
    753
  • Abstract
    A method for effective synthesis of multiple downconversion local oscillator (LO) frequencies within a harmonic rejection mixer (HRM) is presented that employs principles similar to direct digital frequency synthesis. The proposed method reduces the tuning range required of the downconversion oscillator in broadband applications. A passive HRM that implements the proposed LO synthesis method and is robust to both gain and phase mismatch is designed in 130 nm CMOS and covers the 48-860 MHz band with a master clock frequency of 0.77-1.72 GHz. Based on Monte Carlo simulations, while considering device mismatches over a 3σ spread, harmonic rejection better than 63 dB is observed for all selectable LO frequencies.
  • Keywords
    CMOS integrated circuits; direct digital synthesis; mixers (circuits); oscillators; CMOS; bandwidth 48 MHz to 860 MHz; broadband applications; direct digital frequency synthesis; downconversion oscillator; embedded LO synthesis; frequency 0.77 GHz to 1.72 GHz; harmonic rejection mixers; multiple downconversion local oscillator; passive HRM; size 130 nm; Clocks; Frequency synthesizers; Gain; Harmonic analysis; Mixers; Receivers; Time frequency analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
  • Conference_Location
    Boise, ID
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4673-2526-4
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2012.6292129
  • Filename
    6292129