DocumentCode :
3206750
Title :
Performance-aware speculation control using wrong path usefulness prediction
Author :
Lee, Chang Joo ; Kim, Hyesoon ; Mutlu, Onur ; Patt, Yale N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX
fYear :
2008
fDate :
16-20 Feb. 2008
Firstpage :
39
Lastpage :
49
Abstract :
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrong-path (i.e. mis-speculated) instructions. These schemes assume that all wrong-path instructions are useless for processor performance and try to eliminate the execution of all wrong-path instructions. However, wrong-path memory references can be useful for performance by providing prefetching benefits for later correct-path operations. Therefore, eliminating wrong-path instructions without considering the usefulness of wrong-path execution can significantly reduce performance as well as increase overall energy consumption. This paper proposes a comprehensive, low-cost speculation control mechanism that takes into account the usefulness of wrong-path execution, while effectively reducing the energy consumption due to useless wrong-path instructions. One component of the mechanism is a simple, novel wrong-path usefulness predictor (WPUP) that can accurately predict whether or not wrong-path execution will be beneficial for performance. The other component is a novel branch-count based fetch gating scheme that requires very little hardware cost to detect if the processor is on the wrong path. The key idea of our speculation control mechanism is to gate the processor pipeline only if (1) the number of outstanding branches is above a dynamically-determined threshold and (2) the WPUP predicts that wrong-path execution will not be beneficial for performance. Our results show that our proposal eliminates most of the performance loss incurred by fetch gating mechanisms that assume wrong-path execution is useless, thereby both improving performance and reducing energy consumption while requiring very little (51- byte) hardware cost.
Keywords :
multiprocessing systems; pipeline processing; storage management; branch-count; correct-path operations; fetch gating mechanisms; performance-aware speculation control; prefetching benefits; processor pipeline; wasted energy consumption reduction; wrong path usefulness prediction; wrong-path usefulness predictor; Computer architecture; Computer science; Costs; Energy consumption; Energy efficiency; Engines; Hardware; Performance loss; Pipelines; Prefetching;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on
Conference_Location :
Salt Lake City, UT
ISSN :
1530-0897
Print_ISBN :
978-1-4244-2070-4
Type :
conf
DOI :
10.1109/HPCA.2008.4658626
Filename :
4658626
Link To Document :
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