• DocumentCode
    3206770
  • Title

    PaCo: Probability-based path confidence prediction

  • Author

    Malik, Kshitiz ; Agarwal, Mayank ; Dhar, Vikram ; Frank, Matthew I.

  • Author_Institution
    Coordinated Sci. Lab., Univ. of Illinois at Urbana-Champaign, Urbana, IL
  • fYear
    2008
  • fDate
    16-20 Feb. 2008
  • Firstpage
    50
  • Lastpage
    61
  • Abstract
    A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applications like pipeline gating and confidence-based SMT fetch prioritization. Previous work in this domain uses a threshold-and-count predictor, where the number of unresolved, low-confidence branches serves as an estimate of path confidence. This approach is inaccurate since it implicitly assumes that all low-confidence branches have the same mispredict rate, and that high-confidence branches never mispredict. We propose an alternative path confidence predictor designed from first principles, called PaCo, that directly estimates the probability that the processor is on the goodpath, and considers contributions from all branches, both high and low confidence. Even though it uses only modest hardware, PaCo can estimate the processorpsilas goodpath likelihood with very high accuracy, with an RMS error of 3.8%. We show that PaCo significantly outperforms threshold-and-count predictors in pipeline gating and SMT fetch prioritization. In pipeline gating, while the best conventional predictor can reduce badpath instructions executed by 7% with a small loss in performance, PaCo can reduce bad-path instructions by 32% without any performance loss. In SMT fetch prioritization, using PaCo instead of conventional path confidence predictors improves performance by up to 23%, and 5.5% on average.
  • Keywords
    estimation theory; multi-threading; pipeline processing; probability; storage management; PaCo; RMS error; SMT fetch prioritization; fetching; path confidence estimate; path instruction; pipeline gating; probability-based path confidence prediction; processor goodpath likelihood; Bandwidth; Counting circuits; Hardware; Performance loss; Pipelines; Pollution; Proposals; Shift registers; State estimation; Surface-mount technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on
  • Conference_Location
    Salt Lake City, UT
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-2070-4
  • Type

    conf

  • DOI
    10.1109/HPCA.2008.4658627
  • Filename
    4658627