An address generator approach to the hardware implementation of a scalable Pease FFT core

This work discusses a scalable hardware implementation of the Pease FFT algorithm, in which structural regularity from the Kronecker formulation is exploited to perform a complete folding of the transform. An address generator approach is proposed for both data permutation and phase factor scheduling throughout the stages. In this article we briefly review the Pease algorithm in Kronecker products, remarking its regularity. Then we explain how the algorithm was mapped onto hardware. A particular implementation on an FPGA target is described analyzing its resource consumption and computation speed perspectives.