DocumentCode
3207101
Title
Automated microprocessor stressmark generation
Author
Joshi, Ajay M. ; Eeckhout, Lieven ; John, Lizy K. ; Isen, Ciji
Author_Institution
Univ. of Texas at Austin, Austin, TX
fYear
2008
fDate
16-20 Feb. 2008
Firstpage
229
Lastpage
239
Abstract
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management schemes. Typical benchmark suites used in performance evaluation do not stress the processor to its limit though, and current practice in industry is to develop artificial benchmarks that are specifically written to generate maximum processor (component) activity. However, manually developing and tuning so called stressmarks is extremely tedious and time-consuming while requiring an intimate understanding of the processor. A synthetic program that can be tuned to produce a variety of benchmark characteristics would significantly help in addressing this problem by enabling the automatic exploration of the large temperature and power design space. This paper demonstrates that with a suitable choice of only 40 hardware-independent program characteristics related to the instruction mix, instruction-level parallelism, control flow behavior, and memory access patterns, it is possible to generate a synthetic benchmark whose performance relates to that of general-purpose and commercial applications. Leveraging this abstract workload modeling approach, we propose StressMaker, a framework that uses machine learning for the automated generation of stressmarks. A comparison with an exhaustive exploration of a large power design space demonstrates that StressMaker is very effective in automatically generating stressmarks in a limited amount of time.
Keywords
microprocessor chips; performance evaluation; automated microprocessor stressmark generation; control flow behavior; instruction mix; instruction-level parallelism; memory access patterns; performance evaluation; Automatic generation control; Character generation; Cooling; Energy management; Microprocessors; Packaging; Power system management; Temperature; Thermal management; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on
Conference_Location
Salt Lake City, UT
ISSN
1530-0897
Print_ISBN
978-1-4244-2070-4
Type
conf
DOI
10.1109/HPCA.2008.4658642
Filename
4658642
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