• DocumentCode
    3207316
  • Title

    DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors

  • Author

    Gupta, Meeta S. ; Rangan, Krishna K. ; Smith, Michael D. ; Wei, Gu-Yeon ; Brooks, David

  • Author_Institution
    Sch. of Eng. & Appl. Sci., Harvard Univ., Cambridge, MA
  • fYear
    2008
  • fDate
    16-20 Feb. 2008
  • Firstpage
    381
  • Lastpage
    392
  • Abstract
    Increases in peak current draw and reductions in the operating voltage of processors stress the importance of dealing with voltage fluctuations in processors. Noise-margin violations lead to undesired effects, like timing violations, which may result in incorrect execution of applications. Several recent architectural solutions for inductive noise have been proposed that, unfortunately, have a strong correlation to the underlying power-delivery package model and require a feedback loop that is largely constrained by the voltage/current sensor characteristics. The resulting solutions are not robust across a wide range of microprocessor designs and packaging technologies. This paper proposes a Delayed-commit and rollback scheme (DeCoR) that guarantees correctness, insensitive to the package model or the responsiveness of the voltage sensors. In particular, our approach recovers from, rather than attempting to avoid, voltage emergencies. This approach incurs a small performance penalty when compared to an ideal machine that does not have voltage emergencies. We show that explicit checkpoint-recovery schemes, intended to handle infrequent events, e.g., radiation-induced soft errors, suffer from large performance overheads for frequently-occurring voltage emergencies. DeCoR requires very few modifications to modern processor designs, as it leverages the existing store queue and reorder buffers. Unlike conventional designs that conservatively protect all components of the processor from inductive noise with overly-large timing margins, our approach only requires conservative protection of the architected register state and cache write paths.
  • Keywords
    microcomputers; noise; DeCoR; architected register state; cache write paths; checkpoint-recovery schemes; delayed commit; inductive noise; microprocessor; noise-margin violations; processors; rollback mechanism; voltage fluctuations; voltage sensors; Delay; Feedback loop; Microprocessors; Noise robustness; Packaging; Protection; Sensor phenomena and characterization; Stress; Timing; Voltage fluctuations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on
  • Conference_Location
    Salt Lake City, UT
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-2070-4
  • Type

    conf

  • DOI
    10.1109/HPCA.2008.4658654
  • Filename
    4658654