Speculative instruction validation for performance-reliability trade-off

With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi-threading (RMT) is an attractive approach for concurrent error detection. RMT provides complete error coverage, while incurring a significant performance impact because of the redundant thread. Achieving perfect reliability at the expense of a high performance drop is not a good design option for systems where slight vulnerability may still achieve the desired error rates. In this paper, we explore speculative mechanisms to trade-off reliability for performance in RMT. Our basic approach validates the execution of an instruction by comparing its result against the expected result. Only those instructions are redundantly executed for which the validations fail. This mechanism is expected to have a minimal vulnerability impact because it is highly unlikely that an erroneous result matches the expected value. We also propose several extensions to the basic approach that further explore the performance-reliability trade-off design space. A combination of these techniques incur about 10% performance impact and about 0.09% undetected base error rate, compared to about 25% performance impact for RMT with no undetected errors.