A 30mW 10b 250MS/s dual channel SHA-less pipeline ADC in 0.18µm CMOS

A 10-bit 30mW 250MS/s dual-channel SHA-less pipeline ADC with op-amp-sharing between two channels and a new timing scheme to eliminate sampling timing skew is presented in this paper. The proposed timing scheme uses a single-edge sampling clock to achieve double sampling without introducing timing skew. It is applicable to SHA-less ADC front-end and meanwhile allows the first-stage flash comparator and encoder to be operated in the clock idle time without affecting the MDAC settling time. It is also applicable to bottom-plate sampling thus avoiding the signal-dependent charge injection. The proposed op-amp sharing technique with switch-embedded dual-input pair eliminates the memory effects without introducing extra capacitance to the op-amp, facilitating the ADC to operate at high sampling rates. The gain and offset errors between the channels are calibrated in digital domain. Simulation results show that the ADC designed in a 018-μm CMOS process achieves a maximum SNDR of 61.84 dB (ENOB = 9.98) and a peak SFDR of 78.1 dB at 250 MS/s. The ADC core consumes 30 mW at 250 MS/s under a 1.8-V supply voltage.