DocumentCode
3207904
Title
FFT hardware accelerator
Author
Morales, Octavio J.
Author_Institution
Space Tech Corp., Fort Collins, CO, USA
fYear
1988
fDate
21-23 Mar 1988
Firstpage
112
Lastpage
115
Abstract
A novel signal processing architecture is described that performs the fast Fourier transform (FFT) in near-optimum time, with minimal hardware. State-of-the-art circuitry and careful layout support ultrafast operations. The processor is capable of executing several signal processing algorithms utilizing a microprogrammable control unit. Array applications can make convenient use of this dedicated processor as a peripheral number cruncher
Keywords
computerised signal processing; fast Fourier transforms; microprogramming; FFT; hardware accelerator; microprogrammable control unit; near-optimum time; peripheral number cruncher; signal processing; Acceleration; Digital signal processing; Discrete Fourier transforms; Fast Fourier transforms; Finite impulse response filter; Flexible printed circuits; Hardware; Military computing; Signal processing; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'
Conference_Location
Colorado Springs, CO
Type
conf
DOI
10.1109/REG5.1988.15911
Filename
15911
Link To Document