• DocumentCode
    3208064
  • Title

    Reduced-complexity serial min-sum decoding

  • Author

    Uchikawa, Hironori ; Harada, Kohsuke ; Tanabe, Yasuhiko

  • Author_Institution
    R&D Center, Toshiba Corp., Tokyo
  • fYear
    2008
  • fDate
    1-5 Sept. 2008
  • Firstpage
    145
  • Lastpage
    150
  • Abstract
    We propose a complexity-reducing method for serial min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed method is evaluated by computer simulations and shown to reduce the decoding complexity up to 70% compared with conventional serial min-sum decoding with small fractional decibel degradation in error correction performance.
  • Keywords
    error correction codes; iterative decoding; maximum likelihood decoding; reliability; check nodes; computer simulations; error correction; iteration process; log-likelihood-ratio value; reduced complexity; reliability; serial min-sum decoding; Computer simulation; Forward error correction; Hardware; Iterative decoding; Parity check codes; Processor scheduling; Research and development; Scheduling algorithm; Sum product algorithm; Turbo codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Turbo Codes and Related Topics, 2008 5th International Symposium on
  • Conference_Location
    Lausanne
  • Print_ISBN
    978-1-4244-2862-5
  • Electronic_ISBN
    978-1-4244-2863-2
  • Type

    conf

  • DOI
    10.1109/TURBOCODING.2008.4658688
  • Filename
    4658688