Title :
A low-redundancy approach to semi-concurrent error detection in data paths
Author :
Antola, Anna ; Piuri, Vincenzo ; Sami, Mariagiovanna
Author_Institution :
Dept. of Electron. & Inf., Politecnico di Milano, Italy
Abstract :
A high-level synthesis approach is proposed for the design of semi-concurrently self-checking devices; attention is focused on data path design. After identifying the reference architecture against which cost and performances should be evaluated, a simultaneous scheduling-and-allocation algorithm is presented, allowing resource sharing between nominal and checking data paths. The algorithm grants that the required checking periodicity is satisfied while minimizing additional costs in terms of functional units. Risk of error aliasing due to resource sharing is analysed
Keywords :
circuit CAD; data flow graphs; design for testability; error detection; finite state machines; high level synthesis; integrated circuit design; logic testing; redundancy; resource allocation; scheduling; CAD; DFG; checking periodicity; data path design; error aliasing analysis; high-level synthesis; low-redundancy approach; reference architecture identification; resource sharing; self-checking devices; semi-concurrent error detection; simultaneous scheduling/allocation algorithm; Costs; Delay; Error correction; Fault detection; High level synthesis; Read only memory; Redundancy; Resource management; Silicon; System testing;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655866
