Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs

Analog/Mixed-Signal (AMS) Power Systems-on-chip (SOC) require variety of current-based tests to be performed, with large dynamic range: from leakages in micro-ampere levels to high power load regulations and current limit test in multi-ampere levels. Limitations associated with automatic test equipment (ATE) incur high test cost in the form long test times and additional hardware required to multiplex high power resources to device-under-test pins. In our work we propose a framework for forcing and measuring currents on-chip via combo-DFT (built-in current sensor, current DAC, recycling and ATE co-test methodologies) and achieves >;50% reduction in manufacturing test time and 50% reduction in ATE resource requirements.