Title :
A formal description of VHDL-AMS analogue systems
Author_Institution :
Southampton Univ., UK
Abstract :
A formal definition of the general VHDL-AMS analogue system has been proposed to relate the way in which the language affects the specification of a non-linear discontinuous analogue system. It has been suggested to model the break set as a separate system in order to facilitate the interaction between the analogue equation set and the digital abstract machine. The significance of the proposed model is that it may be used in semantic validation of VHDL-AMS description and may also facilitate mixed-signal equation formulation for an underlying VHDL-AMS simulator
Keywords :
analogue integrated circuits; circuit CAD; formal specification; hardware description languages; integrated circuit design; mixed analogue-digital integrated circuits; VHDL-AMS analogue systems; formal description; mixed-signal equation formulation; nonlinear discontinuous analogue system; semantic validation; Delay effects; Differential algebraic equations; Integral equations; Kernel; LAN interconnection; Signal processing; US Department of Transportation;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655968
