Title :
Denotational semantics of a behavioral subset of VHDL
Author_Institution :
Provence Univ., Marseille, France
Abstract :
This paper introduces a denotational semantics of a behavioral subset of VHDL. This subset is restricted to basic data types only and does not allow for clauses in wait statement. We consider the full model of time and resolution, we give a precise definition of the simulation mechanism. Easy translation rules from VHDL to Boyer-Moore logic can be derived from that semantics
Keywords :
computational linguistics; hardware description languages; high level synthesis; Boyer-Moore logic; VHDL; behavioral subset; data type; denotational semantics; simulation; translation rules; wait statement; Computational modeling; Computer architecture; Data structures; Discrete event simulation; Hardware design languages; Signal processing; Signal resolution;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655996
