DocumentCode :
3208727
Title :
RENO: a rename-based instruction optimizer
Author :
Petric, Vlad ; Sha, Tingting ; Roth, Amir
Author_Institution :
Dept. of Comput. & Inf. Sci., Pennsylvania Univ., USA
fYear :
2005
fDate :
4-8 June 2005
Firstpage :
98
Lastpage :
109
Abstract :
RENO is a modified MIPS R10000 register renamer that uses map-table "short-circuiting" to implement dynamic versions of several well-known static optimizations: move elimination, common subexpression elimination, register allocation, and constant folding. Because it implements these optimizations dynamically, RENO can apply optimizations in certain situations where static compilers cannot. Cycle-level simulation shows that RENO dynamically eliminates (i.e. optimizes away) 22% of the dynamic instructions in both SPECint2000 and MediaBench. RENOCF is responsible for 12% and 17% of the eliminations, respectively. Because dataflow dependences are collapsed around eliminated instructions, performance improves by 8% and 13%, respectively. Alternatively, because eliminated instructions do not consume issue queue entries, physical registers, or issue, bypass, register file, and execution bandwidth, RENO can be used to absorb the performance impact of a significantly scaled-down execution core.
Keywords :
data flow computing; instruction sets; optimisation; optimising compilers; storage allocation; MIPS R10000 register renamer; MediaBench; RENO; SPECint2000; common subexpression elimination; constant folding; cycle-level simulation; move elimination; register allocation; rename-based instruction optimizer; static optimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on
ISSN :
1063-6897
Print_ISBN :
0-7695-2270-X
Type :
conf
DOI :
10.1109/ISCA.2005.43
Filename :
1431549
Link To Document :
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