• DocumentCode
    3209176
  • Title

    Piecewise linear branch prediction

  • Author

    Jiménez, Daniel A.

  • Author_Institution
    Dept. of Comput. Sci., Rutgers Univ., USA
  • fYear
    2005
  • fDate
    4-8 June 2005
  • Firstpage
    382
  • Lastpage
    393
  • Abstract
    Improved branch prediction accuracy is essential to sustaining instruction throughput with today´s deep pipelines. We introduce piecewise linear branch prediction, an idealized branch predictor that develops a set of linear functions, one for each program path to the branch to be predicted, that separate predicted taken from predicted not taken branches. Taken together, all of these linear functions form a piecewise linear decision surface. We present a limit study of this predictor showing its potential to greatly improve predictor accuracy. We then introduce a practical implementable branch predictor based on piecewise linear branch prediction. In making our predictor practical, we show how a parameterized version of it unifies the previously distinct concepts of perceptron prediction and path-based neural prediction. Our new branch predictor has implementation costs comparable to current prominent predictors in the literature while significantly improving accuracy. For a deeply pipelined simulated microarchitecture our predictor with a 256 KB hardware budget improves the harmonic mean normalized instructions-per-cycle rate by 8% over both the original path-based neural predictor and 2Bc-gskew. The average misprediction rate is decreased by 16% over the path-based neural predictor and by 22% over 2Bc-gskew.
  • Keywords
    microprogramming; parallel architectures; piecewise linear techniques; pipeline processing; implementable branch predictor; linear functions; path-based neural prediction; path-based neural predictor; perceptron prediction; piecewise linear branch prediction; piecewise linear decision surface; predictor accuracy; simulated microarchitecture; Accuracy; Computer science; Costs; Delay; Hardware; Microarchitecture; Piecewise linear techniques; Pipelines; Predictive models; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on
  • ISSN
    1063-6897
  • Print_ISBN
    0-7695-2270-X
  • Type

    conf

  • DOI
    10.1109/ISCA.2005.40
  • Filename
    1431572