Test synthesis: an innovative approach to analog and system testability analysis using state dependent flow diagrams

Author

Wegener, Steven A.

Author_Institution

Adv. Studies Group, McDonnell Douglas Corp., St. Louis, MO, USA

fYear

1995

fDate

8-10 Aug. 1995

Firstpage

534

Lastpage

543

Abstract

The largest single effort associated with a testability analysis is the creation or modeling of tests. This paper presents a methodology, referred to as Test Synthesis, that automates the process of creating a set of tests that are suitable for performing a testability analysis and developing an initial test strategy. In the context of this paper, a test is defined as: "The acquisition or definition of data that leads to the detection of one or more faults". Test Synthesis combines topological data with testability models to create a comprehensive set of tests with minimal user input.

Keywords

automatic testing; design for testability; diagnostic expert systems; fault diagnosis; flow graphs; high level synthesis; logic CAD; logic testing; AutoTEST program; I/O equation; analog testability analysis; circuit card assemblies; circuit model; design level tests; fault detection; fault isolation; high level model; minimal user input; state dependent flow diagrams; state propagation; system testability analysis; test synthesis; testability models; topological data; Automatic testing; Capacitors; Circuit faults; Circuit synthesis; Circuit testing; Filters; Performance analysis; Performance evaluation; Resistors; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON '95. Systems Readiness: Test Technology for the 21st Century. Conference Record

Conference_Location

Atlanta, GA, USA

Print_ISBN

0-7803-2621-0

Type

conf

DOI

10.1109/AUTEST.1995.522721

Filename

522721