Programmable architecture for matrix and signal processing

A matrix signal processor (MSP) is being developed to provide fast and efficient solutions for several different groups of problems. The design balances the speed of a dedicated pipeline with the generality of a reconfigurable architecture. Throughput, flexibility, and efficiency are maximized by incorporating a programmable pipeline. Additional features are incorporated to increase further the throughput. Dual cache memory banks reduce processor idle time to almost zero while performing back-to-back matrix or signal processing algorithms. A third cache memory bank stores both constant coefficients for such algorithms as the FFT (fast Fourier transform) and temporary coefficients for such algorithms as time-invariant filtering