Title :
High Performance and Parallel Model for LU Decomposition on FPGAs
Author :
Shao, Yi ; Jiang, Liehui ; Zhao, Qiuxia ; Wang, Yuliang
Author_Institution :
Technol. R&D Center, China Nat. Digital Switching Syst. Eng., Zheng Zhou, China
Abstract :
The matrix LU decomposition is the key kernel of the Linpack benchmark. Based on the analysis of the theory Gaussian elimination, this paper proposes a parallel model of implementing the LU decomposition on FPGAs. The model has the pivoting operation and different architecture with former designs. Experimental results show the floating-point performance of our designs achieves 3371.40 MFLOPS at 110 MHz clock frequency, which is 4 times greater than the microprocessor while operating at a clock frequency that is 27 times lower.
Keywords :
field programmable gate arrays; matrix algebra; FPGA; Gaussian elimination; Linpack benchmark; frequency 110 MHz; matrix LU decomposition; Clocks; Computer science; Equations; Field programmable gate arrays; Frequency; Kernel; Matrices; Matrix decomposition; Switching systems; Vectors; Gaussian Elimination; LU decomposition; field programmable gate array (FPGA); parallel; pivoting;
Conference_Titel :
Frontier of Computer Science and Technology, 2009. FCST '09. Fourth International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-0-7695-3932-4
Electronic_ISBN :
978-1-4244-5467-9
DOI :
10.1109/FCST.2009.66
