A power-efficient CMOS active pixel sensor imager with column-level difference ADC in 0.18-µm

In this paper a CMOS active pixel sensor (APS) imager with column-level analog-to-digital converter (ADC) is presented. In conventional column-level ADC imagers, the ADCs are active in the entire readout time intervals. But by using difference ADCs where the difference of consecutive samples is digitized instead of each sample independently, and by noting the fact that the light intensity of neighbouring pixels in a column are usually very close, the single-slope ADCs digitizing the differences are not active in the entire readout intervals leading to considerable saving the power consumption. According to simulation results of the circuit in a 0.18-μm CMOS technology, the proposed imager with 30×40 pixel array and with 8-bit column-level ADCs and 130 frame/s, consumes 830μW where the power consumption of the ADCs and the entire imager are reduced by factors of 10 and 2, respectively.