A power-efficient successive approximation ADC using an improved control logic circuit

In this paper a new control logic circuit for successive approximation register analog-to-digital converter (SA-ADC) is proposed. In the proposed digital circuit architecture, the number of flip-flops is reduced and the flip-flops do not need set and reset nodes. The simulation results of a 5-bit, 100 MS/s ADC in a 0.18-μm technology show that the digital power consumption of the proposed structure is reduced by a factor of 17% and the overall power consumption is reduced around 10% in comparison with the conventional counterpart.