Title :
Low-Latency Implementation of Coordinate Conversion in Virtex II pro FPGA
Author :
Jablonski, G. ; Przygoda, K.
Author_Institution :
Tech. Univ. of Lodz, Lodz
Abstract :
The paper presents a low-latency implementation of Cartesian-polar coordinate conversion in a Virtex II pro FPGA. The accuracy and resource consumption of the module is comparable to the one obtained with the Xilinx CORDIC IP Core, but the latency has been reduced to 65%. The application of the conversion module to the cavity detuning computation in low-level radio frequency control system for a FLASH accelerator has been also presented.
Keywords :
electronic engineering computing; field programmable gate arrays; logic design; table lookup; Cartesian-polar coordinate conversion; FLASH accelerator; Virtex II pro FPGA; Xilinx CORDIC IP Core; cavity detuning computation; low-latency implementation; low-level radio frequency control system; Computer science; Field programmable gate arrays; Microelectronics; Arcus tangent; CORDIC; Computer arithmetic; Cosine; FPGA; Sine; Square root;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
Conference_Location :
Ciechocinek
Print_ISBN :
83-922632-9-4
Electronic_ISBN :
83-922632-9-4
DOI :
10.1109/MIXDES.2007.4286132
