Design of a radiation-hard DDFS

Author

Zhou, Zhihe ; Horowitz, Irwin ; La Rue, George S.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA

fYear

2005

fDate

15-15 April 2005

Firstpage

88

Lastpage

91

Abstract

A radiation hardened direct digital frequency synthesizer (DDFS) was designed in 0.18 mum CMOS technology. A novel 14-bit nonlinear DAC is used to generate sine waves using a piecewise quadratic approximation. The nonlinear DAC effectively reduces lookup table size and total power dissipation. The DDFS is reconfigurable, has built-in automatic calibration and provides quadrature differential outputs. The 32-bit parallel phase accumulator provides 0.5 Hz frequency resolution and incorporates single-event upset (SEU) detection and correction circuitry. Digital and analog circuits are designed using radiation hard by design (RHBD) techniques. Simulation results show that 80 dB SFDR can be achieved for frequencies below 250 MHz at 2 GSps

Keywords

CMOS integrated circuits; digital-analogue conversion; direct digital synthesis; integrated circuit design; radiation hardening (electronics); 0.18 micron; 14 bit; 80 dB; CMOS technology; analog circuits; built-in automatic calibration; digital circuits; direct digital frequency synthesizer; lookup table; nonlinear DAC; parallel phase accumulator; piecewise quadratic approximation; power dissipation; quadrature differential outputs; radiation hard by design; radiation-hard DDFS; sine wave generation; single-event upset correction circuitry; single-event upset detection circuitry; CMOS technology; Calibration; Circuits; Frequency synthesizers; Phase detection; Phase frequency detector; Power dissipation; Radiation hardening; Single event upset; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on

Conference_Location

Boise, ID

Print_ISBN

0-7803-9072-5

Type

conf

DOI

10.1109/WMED.2005.1431629

Filename

1431629