New routing and compaction strategies for yield enhancement

Author

Chiluvuri, Venkat K R ; Koren, Israel

Author_Institution

Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

fYear

1992

fDate

4-6 Nov 1992

Firstpage

325

Lastpage

334

Abstract

Improvements in manufacturing lines alone can not compensate for the yield losses due to the increase in complexity of logic. Manufacturing yield improvement needs to be addressed during the physical layout synthesis stage itself. Several layout strategies for yield enhancement are proposed and they are illustrated with respect to channel compaction and routing in standard cell design. Algorithms and other implementation issues are discussed and examples illustrating these algorithms are presented

Keywords

cellular arrays; circuit layout CAD; logic CAD; network routing; channel compaction; compaction strategies; complexity of logic; layout strategies; manufacturing lines; physical layout synthesis stage; routing; standard cell design; yield enhancement; yield losses; Algorithm design and analysis; Compaction; Computer aided manufacturing; Design automation; Electric variables; Fault tolerant systems; Logic; Minimization methods; Routing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on

Conference_Location

Dallas, TX

ISSN

1550-5774

Print_ISBN

0-8186-2837-5

Type

conf

DOI

10.1109/DFTVS.1992.224342

Filename

224342

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3210487