• DocumentCode
    3210512
  • Title

    A universal self-test design for chip, card and system

  • Author

    Wu, David M. ; Doney, Richard

  • Author_Institution
    Adv. Workstation Div., IBM, Austin, TX, USA
  • fYear
    1992
  • fDate
    4-6 Nov 1992
  • Firstpage
    305
  • Lastpage
    314
  • Abstract
    Describes an implementation of chip built-in self-test using by-pass boundary scan design. This basic structure is then modified to implement a universal self-test structure for cards, boxes and systems
  • Keywords
    automatic testing; boundary scan testing; built-in self test; integrated circuit testing; printed circuit testing; boxes; by-pass boundary scan design; chip built-in self-test; system test; universal self-test design; Automatic testing; Built-in self-test; Circuit testing; Delay; Feeds; Latches; Logic circuits; Logic design; Logic testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
  • Conference_Location
    Dallas, TX
  • ISSN
    1550-5774
  • Print_ISBN
    0-8186-2837-5
  • Type

    conf

  • DOI
    10.1109/DFTVS.1992.224344
  • Filename
    224344
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3210512