Title :
Reconfigurable FPGA-Based Hardware Accelerator for Embedded DSP
Author :
Rubin, G. ; Omieljanowicz, M. ; Petrovsky, A.
Author_Institution :
Bialystok Tech. Univ., Bialystok
Abstract :
This paper presents reconfigurable FPGA-based hardware accelerator for embedded DSP. At first the principle of shared-memory based processor are shown and then specific universal balanced architecture is proposed. An example of processor for TVDFT on the given accelerator is also given. Implementation of multiplier and adder based on the serial arithmetic are included as processor elements.
Keywords :
digital signal processing chips; embedded systems; field programmable gate arrays; memory architecture; TVDFT; adder; embedded DSP; hardware accelerator; multiplier; reconfigurable FPGA; serial arithmetic; shared-memory based processor; universal balanced architecture; Arithmetic; Computer architecture; Costs; Digital signal processing; Digital signal processing chips; Energy consumption; Field programmable gate arrays; Hardware; Read-write memory; Registers; DSP; FPGA; Shared-memory; TVDFT;
Conference_Titel :
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
Conference_Location :
Ciechocinek
Print_ISBN :
83-922632-9-4
Electronic_ISBN :
83-922632-9-4
DOI :
10.1109/MIXDES.2007.4286138
