Distributed Arithmetic Based Implementation of Fourier Transform Targeted at FPGA Architectures

Discrete Fourier transform is recognized as one of the basic digital signal processing operations. One of the most efficient methods of performing this transformation is fast Fourier transform (FFT). It has been showed that no algorithm for computing the DFT could have a smaller complexity than the FFT. Thus most FPGA implementations are based on this approach. With the introduction of specialized DSP blocks embedded into programmable architectures the efficiency of FFT is limited by the speed of hardware multipliers of DSP modules. However, programmable architectures provide possibility to increase the performance of digital system by exploitation of parallelisms of implemented algorithms. In this paper application of distributed arithmetic concept to DFT implementation is described. Results showing the performance improvement in comparison to FFT implementation is shown.