Power reduction techniques in a 6 bit 1 GSPS flash ADC

Flash Analog-to-Digital Converters (ADCs) are usually used in high-speed yet low-resolution applications such as wideband radio transceivers. Since the power consumption of such ADCs exponentially rises with the number of bits, low-power design techniques are of increasing interest. In this work, the power consumption of the comparators, the most important building blocks in such ADCs, have been reduced. First, a modified circuit configuration is proposed where the value of the kick-back noise is remarkably reduced. Then in order to save power, a power reduction technique is presented based on the principle of turning off the preamplifier of the comparators after the time when output voltages have been decided using an XOR gate. Since the difference of the input voltage with the reference level is not very small for most of the comparators in a Flash ADC, most of the comparators´ outputs are ready before the end of the clock period and thus the proposed idea can save up to 40% of the power consumption of the entire ADC. In order to illustrate the effectiveness of the suggested idea, a 6-bit 1GS/s ADC is designed and simulated in a 0.18μm CMOS technology. The circuit consumes 20.2 mW from a 1.8-V supply voltage, and the THD is -32 dB at the input frequency of 200 MHz.