Time redundant error correcting adders and multipliers

Author

Hsu, Yuang-Ming ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1992

fDate

4-6 Nov 1992

Firstpage

247

Lastpage

256

Abstract

Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern

Keywords

adders; error correction; multiplying circuits; redundancy; Duplication With Comparison; REDWC; REcomputing; error correcting adders; error correction; error-detecting adder; fault-tolerance; hardware complexity; multipliers; time redundancy; Adders; Application software; Circuits; Computer errors; Costs; Delay; Error correction; Fault tolerance; Hardware; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on

Conference_Location

Dallas, TX

ISSN

1550-5774

Print_ISBN

0-8186-2837-5

Type

conf

DOI

10.1109/DFTVS.1992.224350

Filename

224350