A low-power low-area architecture design for distributed arithmetic (DA) unit

In this paper an improved DA architecture is proposed. In the proposed DA, the high power consumption adder units are relocated in the system to lower the switching activity and total power. The proposed DA exploits the circuit activity and the adder units are only used just in minimum states. The designed DA is a run-time reconfigurable. The design is verified, and simulation results via 2-phase power calculations based on forward synthesis invariant approach and back ward synthesis oriented activity approach is used to calculate the power and area of the proposed DA and all known counterparts. In the experimental results on 180n CMOS ASIC synthesis the maximum clock of 180 MHz is achieved. In the 5-tape FIR filter implementation of our proposed DA with clock gating enabled and best known LUT Less2, the dynamic power and area improvements are 39.76% and 16.35% respectively.