DocumentCode
3210760
Title
A Low-Power Strategy for Delta-Sigma Modulators
Author
Pesenti, S. ; Clement, P. ; Stefanovic, D. ; Kayal, M.
Author_Institution
Marvell Semicond., Etoy
fYear
2007
fDate
21-23 June 2007
Firstpage
203
Lastpage
208
Abstract
This paper presents a hybrid continuous-discrete-time delta-sigma modulator for portable communication systems following a low-power strategy. The proposed design methodology is extendable to different specifications. A multi-bit technique has been introduced in an efficient manner to optimize the power consumption, and an adaptive algorithm is used to allow for a 3-fold reduction in the number of comparators.
Keywords
comparators (circuits); continuous time systems; delta-sigma modulation; discrete time systems; modulators; power consumption; comparators; delta-sigma modulators; hybrid continuous-discrete-time delta-sigma modulator; low-power strategy; portable communication systems; power consumption; CMOS technology; Clocks; Delta modulation; Design methodology; Energy consumption; Feedback; Frequency; Noise shaping; Quantization; Sampling methods; Auto-ranging algorithm; Delta-Sigma modulator; Mismatch shaping encoder; Multi-bit;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
Conference_Location
Ciechocinek
Print_ISBN
83-922632-9-4
Electronic_ISBN
83-922632-9-4
Type
conf
DOI
10.1109/MIXDES.2007.4286151
Filename
4286151
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