DocumentCode
3210811
Title
On fault probabilities and yield models for analog VLSI neural networks
Author
Furth, Paul M. ; Andreou, Andreas G.
Author_Institution
Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
fYear
1992
fDate
4-6 Nov 1992
Firstpage
167
Lastpage
176
Abstract
Investigates the estimation of fault probabilities and yield for analog VLSI implementations of neural computation. The analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. The work improves on the framework suggested recently by Feltham and Maly (1991) and is also applicable to analog or mixed analog/digital VLSI systems
Keywords
VLSI; analogue processing circuits; mixed analogue-digital integrated circuits; neural chips; probability; analog VLSI neural networks; distributed parallel processing systems; fault probabilities; mixed analog/digital VLSI systems; yield models; Circuit faults; Computer networks; Fault diagnosis; Fault tolerant systems; Neural networks; Semiconductor device modeling; Silicon; System performance; Very large scale integration; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
Conference_Location
Dallas, TX
ISSN
1550-5774
Print_ISBN
0-8186-2837-5
Type
conf
DOI
10.1109/DFTVS.1992.224358
Filename
224358
Link To Document