Comparison of Two Pole-Zero Cancellation Circuits for Fast Charge Sensitive Amplifier in CMOS Technology

The problem of charge sensitive amplifier and pole-zero cancellation circuit designed in CMOS technology for high rates of input pulses is considered. The continuously sensitive charge amplifier uses a MOS transistor biased in triode region to discharge the integration capacitance. Low noise requirements of the front-end electronics place the feedback CSA resistance in hundreds of the megaohm range. However the high counting rate of input pulses generates a DC voltage shift at the CSA output which could degrade the circuit performance. We analyze two circuit architectures for biasing transistors in feedback of CSA and PZC circuit taking into account the pile-up effects in the signal processing chain.