DocumentCode
3211018
Title
Bridging faults modeling and detection in CMOS combinational gates
Author
Buonanno, Giacomo ; Sciuto, Donatella
Author_Institution
Dipartimento di Elettronica, Politecnico di Milano, Italy
fYear
1992
fDate
4-6 Nov 1992
Firstpage
80
Lastpage
89
Abstract
A method based on the detectability of bridging faults through test sets developed to locate other types of faults is presented. In particular it will be shown how bridging faults can be detected in CMOS combinational circuits using a test procedure that detects transistor stuck-at faults in a new design for testability for fully CMOS logic. The detection of more than 95% of the possible bridging faults (single and multiple) is achieved
Keywords
CMOS integrated circuits; combinatorial circuits; fault location; logic gates; logic testing; CMOS combinational gates; bridging faults; detectability; test procedure; test sets; testability; transistor stuck-at faults; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Design for testability; Electrical fault detection; Fault detection; Logic design; Logic testing; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
Conference_Location
Dallas, TX
ISSN
1550-5774
Print_ISBN
0-8186-2837-5
Type
conf
DOI
10.1109/DFTVS.1992.224371
Filename
224371
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