Title :
Time complexity of systolic array testing
Author :
Faroughi, Nikrouz
Author_Institution :
Dept. of Comput. Sci., California State Univ., Sacramento, CA, USA
Abstract :
The testing time for a C-testable orthogonal iterative systolic array (OISA) is derived where no knowledge on cell functions are assumed. The test inputs are regenerated as inputs for some inner cells at some future times at known distances (regeneration distances) from the outputs of those cells which are currently being tested. For minimum test time, it is required that the test input with maximum regeneration distance be applied last. For the non-OISAs, reconfigurable functional routers in each cell is proposed. A non-OISA can be reconfigured into one or more OISAs
Keywords :
cellular arrays; computational complexity; iterative methods; logic testing; systolic arrays; C-testable orthogonal iterative systolic array; cell functions; minimum test time; reconfigurable functional routers; regeneration distances; systolic array testing; Circuit faults; Circuit testing; Communication system control; Computer science; Controllability; Observability; Pipelines; Systolic arrays;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2837-5
DOI :
10.1109/DFTVS.1992.224373
