Implementation of Cholesky LLT-Decomposition Algorithm in FPGA-Based Rational Fraction Parallel Processor

Author

Maslennikow, O. ; Ratuszniak, P. ; Sergyienko, A.

Author_Institution

Tech. Univ. of Koszalin, Koszalin

fYear

2007

fDate

21-23 June 2007

Firstpage

287

Lastpage

292

Abstract

In this paper, the fixed size processor array architecture, which is destined for realization of LL^T-decomposition of symmetrical positively definite matrices based on Cholesky algorithm, is proposed. In order to implementation of this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. This AU is adapted to realization in the Xilinx reconfigurable platforms Virtex II or Virtex 4 families and its hardware complexity is up to 4,5 times less in comparison with similar AUs operating with float-point numbers.

Keywords

field programmable gate arrays; floating point arithmetic; matrix decomposition; parallel architectures; Cholesky LL^T-decomposition algorithm; FPGA-based rational fraction parallel processor; Virtex 4 family; Virtex II family; Xilinx reconfigurable platform; arithmetic unit; fixed size processor array architecture; float-point numbers; Algorithm design and analysis; Arithmetic; Digital signal processing; Field programmable gate arrays; Gold; Hardware; Linear algebra; Pipeline processing; Problem-solving; Signal processing algorithms; FPGA; Linear algebra algorithm; Rational fraction arithmetic; Rational fraction number system; VLSI array processor;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on

Conference_Location

Ciechocinek

Print_ISBN

83-922632-9-4

Electronic_ISBN

83-922632-9-4

Type

conf

DOI

10.1109/MIXDES.2007.4286169

Filename

4286169