Lessons learnt from designing a wafer scale 2D array

Author

Boubekeur, A. ; Patry, J.L. ; Saucier, G. ; Slimane-kadi, M. ; Trilhe, J.

Author_Institution

Inst. Nat. Polytech. de Grenoble, France

fYear

1992

fDate

4-6 Nov 1992

Firstpage

137

Lastpage

146

Abstract

Describes how defect tolerance is achieved for a wafer scale architecture that has been implemented on silicon. It gives an overview of a long-term research effort and describes software methods and tools as well as hardware switching devices used to create a defect free 2D array at end of manufacturing. This wafer scale architecture is called ELSA (European Large SIMD Array) and has been studied within an ESPRIT project on wafer scale integration

Keywords

VLSI; circuit CAD; parallel architectures; systolic arrays; CAD; ELSA; ESPRIT project; European Large SIMD Array; defect free 2D array; defect tolerance; hardware switching devices; software methods; wafer scale 2D array; Circuits; Hardware; Manufacturing; Proposals; Registers; Silicon; Switches; Testing; Transistors; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on

Conference_Location

Dallas, TX

ISSN

1550-5774

Print_ISBN

0-8186-2837-5

Type

conf

DOI

10.1109/DFTVS.1992.224377

Filename

224377

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3211113