• DocumentCode
    3211243
  • Title

    Reducing BIST hardware by test schedule optimization

  • Author

    Stroele, Albrecht P.

  • Author_Institution
    Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
  • fYear
    1992
  • fDate
    26-27 Nov 1992
  • Firstpage
    253
  • Lastpage
    258
  • Abstract
    VLSI circuits are segmented using built-in self-test registers. During the test execution a signature is collected for each of the subcircuits. The author presents a set of test scheduling algorithms that minimize the hardware overhead required for test control and test evaluation under different restrictions. The subcircuit tests are ordered such that only a subset of the signatures must be scanned and evaluated at the end of the test. The algorithms allow a tradeoff between test time and test hardware overhead
  • Keywords
    VLSI; built-in self test; integrated circuit testing; integrated logic circuits; logic testing; optimisation; scheduling; BIST; IC testing; VLSI; built-in self-test registers; logic testing; signatures; test control; test evaluation; test schedule optimization; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Hardware; Logic testing; Optimal scheduling; Registers; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
  • Conference_Location
    Hiroshima
  • Print_ISBN
    0-8186-2985-1
  • Type

    conf

  • DOI
    10.1109/ATS.1992.224399
  • Filename
    224399