PMOS drain breakdown voltage walk-in: a new failure mode in high power BiCMOS applications

Author

Brisbin, Douglas ; Strachan, Andy ; Chaparala, Prasad

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

2004

fDate

25-29 April 2004

Firstpage

265

Lastpage

268

Abstract

High voltage power management applications often require 50V to 100V operation. These circuits are implemented in a BiCMOS processes and support both low voltage (5-15V) and high voltage devices. In these applications the high voltage PMOS (HV-PMOS) must operate at high currents, voltages (e.g. 80V) and temperatures (150°C) while sustaining a drain breakdown voltage in excess of the device operating voltage. This paper examines an HV-PMOS failure mode identified during device qualification and high temperature operational life. This paper presents data on a new PMOS failure mechanism termed "drain breakdown voltage walk-in" not yet discussed in the literature.

Keywords

BiCMOS integrated circuits; electric breakdown; failure analysis; integrated circuit reliability; power integrated circuits; 150 C; 5 to 15 V; 50 to 100 V; 80 V; PMOS drain breakdown voltage walk-in; device operating voltage; failure mode; high power BiCMOS applications; BiCMOS integrated circuits; Breakdown voltage; Displays; Energy management; Failure analysis; Implants; Low voltage; Qualifications; Stress; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International

Print_ISBN

0-7803-8315-X

Type

conf

DOI

10.1109/RELPHY.2004.1315335

Filename

1315335