A test application scheme for embedded full-scan circuits to reduce testing costs

The authors present a method to reduce test storage and test application time for stored-pattern testing in embedded full-scan circuits, without compromising the fault coverage. A combination of stored-pattern and built-in test is proposed to reduce the test storage and test application time by shifting output patterns back to the inputs of the circuit (similar to circular BIST), using the output responses of the circuit as additional test patterns. The circuit operates in such an autonomous mode as long as new faults can be detected. Externally applied, or stored, patterns are used to initialize the autonomous test application phase to maximize the fault coverage each phase achieves, and minimize the number of phases required