Hardware Fault Free Simulation for SOC

Author

Hahanov, V.I. ; Kaminska, M.O. ; Ghribi, W. ; Hahanova, A.V.

Author_Institution

Kharkiv Nat. Univ. of Radioelectron., Kharkiv

fYear

2007

fDate

21-23 June 2007

Firstpage

424

Lastpage

428

Abstract

In the paper structure functional multi-valued hardware model of digital device is offered; two-circuits structure functional multi-valued hardware model of digital device for multiple input patterns co-simulation and multiple increasing of performance transient analysis in sequential structures is proposed; automatic model of HDL-code transmission process to data structure for digital system on chip analysis and verification with hardware is proposed.

Keywords

data structures; digital circuits; hardware description languages; hardware-software codesign; system-on-chip; transient analysis; HDL-code transmission process; SOC; data structure; digital device; digital system onchip analysis; hardware description language; hardware fault free simulation; hardware verification; multiple input patterns cosimulation; sequential structure; structure functional multivalued hardware model; system-on-chip; transient analysis; Analytical models; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Discrete event simulation; Hardware; Hazards; Mathematical model; System testing; Fault simulation; Hardware embedded simulator; Test generation; Topological analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on

Conference_Location

Ciechocinek

Print_ISBN

83-922632-9-4

Electronic_ISBN

83-922632-9-4

Type

conf

DOI

10.1109/MIXDES.2007.4286197

Filename

4286197