DocumentCode :
3211571
Title :
Functional simulation using binary decision diagrams
Author :
Scholl, C. ; Drechsler, R. ; Becker, B.
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
fYear :
1997
fDate :
9-13 Nov. 1997
Firstpage :
8
Lastpage :
12
Abstract :
In many verification techniques, fast functional evaluation of a Boolean network is needed. We investigate the idea of using binary decision diagrams (BDDs) for functional simulation. The area-time trade-off that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow smaller representations with (nearly) no runtime penalty.
Keywords :
circuit analysis computing; digital simulation; directed graphs; integrated circuit modelling; minimisation; BDDs; Boolean network; area-time trade-off; binary decision diagrams; dynamic reordering; fast functional evaluation; functional simulation; minimization techniques; verification techniques; Circuit simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-8186-8200-0
Type :
conf
DOI :
10.1109/ICCAD.1997.643253
Filename :
643253
Link To Document :
بازگشت