C-V and C-P characterization sensitivities for fast and slow-state traps in very thin oxide MOSFETs

The present experiments are intended to evaluate the limited sensitivity to characterize defects in very thin oxide MOSFET transistors at its Si/SiO₂ interface using temperature-dependent capacitance-voltage measurements (TDCV) Charge-pumping method (C-P) has also been considered for thinner oxides. The TDCV method has the advantage to investigate defect properties at cryogenic temperatures and to introduce simultaneously an insight for high temperature-activated processes. By these high-frequency C-V measurements, the comparison of two kinds of traps occurring at the interface Si/SiO₂ has been performed on especially 53 nm thick oxide MOSFET samples. It is shown to be useful in analyzing low defect densities. Sensitivity by TDCV reaches its lowest value for h-f C-V, which is D_fs = 10⁹ cm^-2 eV^-1 for fast state and N_ss = 10⁸ cm^-2 for slow state traps. C-P can also reach a good sensitivity in the upper 10⁹ cm^-2 eV^-1 range. Fast-state and slow-state trap cross-sections are calculated and a linear generation of defects is found at low temperature. A correlation with the SILC (Stress Induced Leakage Current) is discussed for less than 4 nm oxide thickness.