• DocumentCode
    3211747
  • Title

    CPLD Based Development Board for Mixed Signal Chip Testing

  • Author

    Sniatala, P. ; Pierzchlewski, J. ; Handkiewicz, A. ; Nowakowski, B.

  • Author_Institution
    Poznan Univ. of Technol., Poznan
  • fYear
    2007
  • fDate
    21-23 June 2007
  • Firstpage
    492
  • Lastpage
    495
  • Abstract
    This paper presents an original testing board dedicated for SI ASIC chips. The board is based on a programmable logic device, which generates the required signals for the tested chip. The parameters of the signals are set with a simple interface. The project was written in a VHDL and implemented in Xilinx CPLD. The board was used to test a new structure of a SI integrator, and the results are also presented.
  • Keywords
    integrated circuit testing; mixed analogue-digital integrated circuits; programmable logic devices; CPLD; SI ASIC chips; VHDL; mixed signal chip testing; programmable logic device; Application specific integrated circuits; Circuit testing; Clocks; Diodes; Field programmable gate arrays; Frequency; Prototypes; Semiconductor device measurement; Signal generators; User interfaces; CPLD; SI; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
  • Conference_Location
    Ciechocinek
  • Print_ISBN
    83-922632-9-4
  • Electronic_ISBN
    83-922632-9-4
  • Type

    conf

  • DOI
    10.1109/MIXDES.2007.4286212
  • Filename
    4286212
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3211747