Custom topology generation for network-on-chip

This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces. An analytical model is used to determine communication latencies in the network-on-chip.