Title :
A current testing for CMOS logic circuits applying random patterns and monitoring dynamic power supply current
Author :
Tamamoto, Hideo ; Yokoyama, Hiroshi ; Narita, Yuichi
Author_Institution :
Dept. of Inf. Eng., Akita Univ., Japan
Abstract :
Assuming a stuck-at fault and stuck-open fault, the authors discussed a random current testing for CMOS logic circuits by monitoring a dynamic power supply current. Random patterns are generated using a modified LFSR, where the outputs of a CUT are fed back to an LFSR. This modification is intended for amplifying the influence of a fault near a primary outputs on the dynamic current. Simulation results showed that the modified LFSR works well for detectability, and a high fault coverage can be obtained applying a small number of test vectors
Keywords :
CMOS integrated circuits; digital simulation; electric current measurement; fault location; integrated circuit testing; integrated logic circuits; power supplies to apparatus; random processes; shift registers; CMOS logic circuits; current testing; detectability; dynamic power supply current; fault coverage; linear feedback shift register; modified LFSR; random patterns; stuck-at fault; stuck-open fault; test vectors; CMOS logic circuits; Circuit faults; Circuit testing; Current supplies; Electrical fault detection; Fault detection; Logic testing; Monitoring; Performance evaluation; Power supplies;
Conference_Titel :
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location :
Hiroshima
Print_ISBN :
0-8186-2985-1
DOI :
10.1109/ATS.1992.224438
