Practical considerations in ATPG using CrossCheck technology

Author

Chandra, Susheel ; Jacobson, Neil ; Srinath, Gopal

Author_Institution

CrossCheck Technol. Inc., San Jose, CA, USA

fYear

1992

fDate

26-27 Nov 1992

Firstpage

88

Lastpage

93

Abstract

The authors deal with some of the practical considerations that arise in porting ATPG patterns to the tester. Issues such as races, bidirectional pins, three-state buses and asynchronous circuits are discussed. Algorithm for dealing with these constructs during the test pattern generation phase are presented. Patterns that correctly handle such situations are easily ported to the tester. Experimental results on real circuits are presented. The results also include ATE resources such as tester time and memory required for the test program. The circuits are assumed to adhere to the CrossCheck design-for-testability methodology

Keywords

automatic test equipment; automatic testing; logic design; logic testing; ASIC; ATE; ATPG; CrossCheck technology; asynchronous circuits; bidirectional pins; design-for-testability; fault simulation; memory; races; test pattern generation; three-state buses; Application specific integrated circuits; Automatic test pattern generation; Circuit faults; Circuit testing; Design methodology; Jacobian matrices; Logic; Macrocell networks; Pins; Probes;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)

Conference_Location

Hiroshima

Print_ISBN

0-8186-2985-1

Type

conf

DOI

10.1109/ATS.1992.224441

Filename

224441